1. Field of the Invention
The present invention relates to a method of erasing a memory device, and more particularly to a method of erasing a memory device which can prohibit a current flow from a drain region to a silicon substrate by applying a low voltage and applying a normal erasure voltage sequentially to the drain region.
2. Description of the Prior Arts
Generally, in a flash memory, a tunneling phenomenon is used to erase a cell. That is, as shown in FIG. 1, a voltage of -13V is applied to a control gate 5, a voltage of 5V is applied to a drain region 3, and a source region 2 is floated. Therefore, the electrons stored at the floating gate 4 go out to the drain region 3, the memory cell is erased.
At this time, when voltage of 5V is applied to the drain region 3 and a voltage of -13V is applied to the control gate 5, holes generated at the drain region 3 go out to the substrate 1 due to its property of moving toward a lowest energy level and an electric field formed between the drain region 3 and the substrate 1. Therefore, a current flows excessively from the drain region 3 to the substrate 1 (hereinafter, called as "BTBT current: band to band tunneling current), the BTBT current prevents a smooth erasure of a device.